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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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SP6134H Arkusz danych(PDF) 7 Page - Exar Corporation |
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SP6134H Arkusz danych(HTML) 7 Page - Exar Corporation |
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7 / 15 page  S SP P6 61 13 34 4H H H Hiig gh h V Vo olltta ag ge e,, 6 60 00 0k kH Hz z S Sy yn nc ch hrro on no ou us s P PW WM M S Stte ep p D Do ow wn n C Co on nttrro olllle err © 2008 Exar Corporation 7/15 Rev. 2.0.0 monitors the positive and negative terminals of the error amplifier, and if the VFB pin ever falls more than 250mV (typical) below the positive reference, a short-circuit fault is set. Because the SS pin overrides the internal 0.8V reference during soft start, the SP6134H is capable of detecting short-circuit faults throughout the duration of soft start as well as in regular operation. HANDLING OF FAULTS Upon the detection of power (UVLO), thermal, or short-circuit faults, the SP6134H is forced into an idle state where the SS and COMP pins are pulled low and the gate drivers are held off. In the event of UVLO fault, the SP6134H remains in this idle state until the UVLO fault is removed. Upon the detection of a thermal or short-circuit fault, an internal 200ms (typical) timer is activated. In the event of a short- circuit fault, a restart is attempted immediately after the 200ms timeout expires. Whereas, when a thermal fault is detected the 200ms delay continuously recycles and a restart cannot be attempted until the thermal fault is removed and the timer expires. ERROR AMPLIFIER AND VOLTAGE LOOP As stated before, the heart of the SP6134H voltage error loop is a high performance, wide bandwidth transconductance amplifier. Because of the amplifier’s current limited (±150μA) transconductance, there are many ways to compensate the voltage loop or to control the COMP pin externally. A simple, single pole, single zero compensation can be a RC to ground. However Exar recommends a Type II or Type III compensation which eliminates the gm of the amplifier from the control loop equations. The amplifier has enough bandwidth (45° at 4 MHz) and enough gain (60dB) to run Type III compensation schemes with adequate gain and phase margins at cross over frequencies greater than 50kHz. The common mode output of the error amplifier is 0.9V to 2.2V. Therefore, the PWM voltage ramp has been set between 1.1V and 2.2V to ensure proper 0% to 100% duty cycle capability. The voltage loop also includes two other very important features. One is an Non- synchronous start up mode. Basically, the GL driver can not turn on unless the GH driver has attempted to turn on or the SS pin has exceeded 1.7V. This feature prevents the controller from “dragging down” the output voltage during startup or in fault modes. The second feature is a 100% duty cycle timeout that ensures synchronized refreshing of the BST capacitor at very high duty ratios. In the event that the GH driver is on for 20 continuous clock cycles, a reset is given to the PWM flip flop half way through the 21st cycle. This forces GL to rise for the remainder of the cycle, in turn refreshing the BST capacitor. GATE DRIVERS The SP6134H contains a pair of powerful 2Ω SOURCE and 1.5Ω SINK drivers. These state of the art drivers are designed to drive external NFETs capable of handling up to 30A. Rise, fall, and non-overlap times have all been minimized to achieve maximum efficiency. All drive pins GH, GL & SWN are monitored continuously to ensure that only one external NFET is ever on at any given time. |
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