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STM32F107RC Arkusz danych(PDF) 72 Page - STMicroelectronics |
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STM32F107RC Arkusz danych(HTML) 72 Page - STMicroelectronics |
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72 / 95 page  Electrical characteristics STM32F105xx, STM32F107xx 72/95 Doc ID 15274 Rev 4 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 31 or Figure 32, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 31. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are available only on 100-pin packages. Figure 32. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ and VREF– inputs are available only on 100-pin packages. V REF+ STM32F10xxx V DDA V SSA/V REF- 1 µF // 10 nF 1 µF // 10 nF ai14380c (See note 1) (See note 1) VREF+/VDDA STM32F10xxx 1 µF // 10 nF VREF–/VSSA ai14381c (See note 1) (See note 1) |
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