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MB90F334APMC Arkusz danych(PDF) 15 Page - fujitsu semiconductor |
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MB90F334APMC Arkusz danych(HTML) 15 Page - fujitsu semiconductor |
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15 / 72 page ![]() MB90330A Series DS07-13734-7E 15 ■ HANDLING DEVICES 1. Preventing latch-up and turning on power supply Latch -up may occur on CMOS IC under the following conditions: • If a voltage higher than VCC or lower than VSS is applied to input and output pins. • A voltage higher than the rated voltage is applied between VCC pin and VSS pin. • If the AVCC power supply is turned on before the VCC voltage. Ensure that you apply a voltage to the analog power supply at the same time as VCC or after you turn on the digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as VCC and the digital power supply). If latch-up occurs, the supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let any voltage exceed the maximum rating. 2. Treatment of unused pins Leaving unused input pins unconnected can cause abnormal operation or latch -up, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k Ω. Any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open. 3. Treatment of power supply pins on models with A/D converters Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC, and AVSS = VSS. 4. About the attention when the external clock is used Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or when recovering from sub clock or stop mode. When suing an external clock, 25 MHz should be the upper frequency limit. The following figure shows a sample use of external clock signals. 5. Treatment of power supply pins (VCC/VSS) In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC pin and VSS pin near this device. X0 X1 OPEN • Using external clock |
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