ACT8798 datasheet(4/34 Pages) ACTIVE-SEMI

4 / 34 page

ACT8798

Rev0, 10-Oct-08

Innovative Power

- 4 -

www.active-semi.com

ActivePMU

TM is a trademark of Active-Semi.

2CTM is a trademark of Philips Electronics.

PIN DESCRIPTIONS

NAME

DESCRIPTION

OUT4

Output Voltage for REG4. Capable of delivering up to 250mA of output current. The output is dis-

charged to G with 650Ω load when disabled.

SCL

Clock Input for I2C Serial Interface. Data is read on the rising edge of the clock.

SDA

Data Input for I2C Serial Interface. Data is read on the rising edge of the clock.

4, 17

Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP12, and GP3 together

at a single point as close to the IC as possible.

nMSTR

Master Enable Input. Drive nMSTR to GA or to a logic low to enable the IC. REG1, REG2, and

REG3 are enabled while nMSTR is asserted.

nRSTO

Open-Drain Reset Output. nRSTO asserts low for the reset timeout period of 300ms whenever the

IC is enabled.

OUT1

Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the inter-

nal feedback network to the output voltage.

VP1

Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed as close as

possible to the IC.

SW1

Switching Node Output for REG1. Connect this pin to the switching end of the inductor.

GP12

Power Ground for REG1 and REG2. Connect GA, GP12, and GP3 together at a single point as

close to the IC as possible.

SW2

Switching Node Output for REG2. Connect this pin to the switching end of the inductor.

VP2

Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed as close as

possible to the IC.

OUT2

Output Feedback Sense for REG2. Connect this pin directly to the output node to connect the inter-

nal feedback network to the output voltage.

ON3

Enable Input for REG3, ON3 is functional only when PWRHLD is driven high. Drive ON3 to a logic

high to turn on the REG3. Drive ON3 to a logic low to turn off the REG3.

PWRHLD

Power Hold Input. Drive PWRHLD to logic high to enable the IC. Drive PWRHLD to a logic low to

disable all regulators.

REFBP

Reference Noise Bypass. Connect a 0.01µF ceramic capacitor from REFBP to GA. This pin is dis-

charged to GA in shutdown.

OUT3

Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the inter-

nal feedback network to the output voltage.

VP3

Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close as

possible to the IC.

SW3

Switching Node Output for REG3. Connect this pin to the switching end of the inductor.

GP3

Power Ground for REG3. Connect GA, GP12, and GP3 together at a single point as close to the IC

as possible.

OUT5

Output Voltage for REG5. Capable of delivering up to 250mA of output current. The output is dis-

charged to G with 650Ω load when disabled.

OUT6

Output Voltage for REG6. Capable of delivering up to 250mA of output current. The output is dis-

charged to G with 650Ω load when disabled.

INL

Power Input for REG4, REG5 and REG6. Bypass to GA with a high quality ceramic capacitor

placed as close as possible to the IC.

Exposed Pad. Must be soldered to ground on PCB.

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