SC9RS08KA2 datasheet(97/134 Pages) FREESCALE

97 / 134 page

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

Chapter 12

Development Support

12.1

Introduction

Development support systems in the RS08 family include the RS08 background debug controller (BDC).

The BDC provides a single-wire debug interface to the target MCU. This interface provides a convenient

means for programming the on-chip FLASH and other nonvolatile memories. Also, the BDC is the

primary debug interface for development and allows non-intrusive access to memory data and traditional

debug features such as CPU register modify, breakpoint, and single-instruction trace commands.

In the RS08 Family, address and data bus signals are not available on external pins. Debug is done through

commands fed into the target MCU via the single-wire background debug interface, including resetting the

device without using a reset pin.

Figure 12-1. Connecting MCU to Host for Debugging

12.2

Features

Features of the RS08 background debug controller (BDC) include:

•

Uses a single pin for background debug serial communications

•

Non-intrusive of user memory resources; BDC registers are not located in the memory map

•

SYNC command to determine target communications rate

•

Non-intrusive commands allow access to memory resources while CPU is running user code

without stopping applications

•

Active background mode commands for CPU register access

•

GO and TRACE1 commands

•

BACKGROUND command can wake CPU from wait or stop modes

MCU

USER PCB

COMMAND TRANSLATOR

TARGET

RS08 POD

HOST

RS-232

USB, Ethernet

SC9RS08KA2 Arkusz danych(PDF) 97 Page - Freescale Semiconductor, Inc