SC9RS08KA2J3CSC datasheet(79/134 Pages) FREESCALE

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Internal Clock Source (RS08ICSV1)

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

9.3.3

ICS Trim Register (ICSTRM)

9.3.4

ICS Status and Control (ICSSC)

432

TRIM

POR:

Reset:

UUU

Figure 9-5. ICS Trim Register (ICSTRM)

Table 9-4. ICSTRM Field Descriptions

Field

Description

7:0

TRIM

ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal

reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).

Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.

An additional fine trim bit is available in ICSSC as the FTRIM bit.

432

CLKST

FTRIM

POR:

Reset:

= Unimplemented

Figure 9-6. ICS Status and Control Register (ICSSC)

Table 9-5. ICSSC Field Descriptions

Field

Description

CLKST

Clock Mode Status — The CLKST read-only bit indicate the current clock mode. The CLKST bit does not update

immediately after a write to the CLKS bit due to internal synchronization between clock domains.

0 Output of FLL is selected

1 Internal reference clock is selected

FTRIM

ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.

Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount

possible.

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