MPC8533ECHXALJB datasheet(90/116 Pages) FREESCALE

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MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

Clocking

19 Clocking

This section describes the PLL configuration of the MPC8533E . Note that the platform clock is identical

to the core complex bus (CCB) clock.

19.1

Clock Ranges

Table 58 provides the clocking specifications for the processor cores and Table 59 provides the clocking

specifications for the memory bus.

19.2

CCB/SYSCLK PLL Ratio

The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform

clock. The frequency of the CCB is set using the following reset signals (see Table 60):

•

SYSCLK input signal

•

Binary value on LA[28:31] at power up

Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note

that the DDR data rate is the determining factor in selecting the CCB bus frequency, since the CCB

frequency must equal the DDR data rate.

Table 58. Processor Core Clocking Specifications

Characteristic

Maximum Processor Core Frequency

Unit

Notes

667 MHz

800 MHz

1000 MHz

1067 MHz

Min

Max

Min

Max

Min

Max

Min

Max

e500 core processor frequency

667

800

667

1000

667

1067

MHz

1, 2

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio settings.

2. The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.

Table 59. Memory Bus Clocking Specifications

Characteristic

Maximum Processor Core

Frequency

Unit

Notes

667, 800, 1000, 1067 MHz

Min

Max

Memory bus clock speed

166

266

MHz

1, 2

Notes:

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio

settings.

2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.

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