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MPC8533ECHXAAJB Arkusz danych(PDF) 51 Page - Freescale Semiconductor, Inc |
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MPC8533ECHXAAJB Arkusz danych(HTML) 51 Page - Freescale Semiconductor, Inc |
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51 / 116 page ![]() MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 51 Programmable Interrupt Controller Figure 29. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Bypass Mode) 11 Programmable Interrupt Controller In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain the assertion for at least 3 system clocks (SYSCLK periods). tLBIXKL2 tLBIVKH1 Internal Launch/Capture Clock UPM Mode Input Signal: LUPWAIT T1 T3 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] GPCM Mode Output Signals: LCS[0:7]/LWE T2 T4 Input Signals: LAD[0:31]/LDP[0:3] LCLK tLBKLOV1 tLBKLOZ1 tLBKLOX1 tLBIXKH1 GPCM Mode Input Signal: LGTA tLBIVKL2 |
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