CPC7582MATR datasheet(18/19 Pages) CLARE

18 / 19 page

CPC7582

www.clare.com

R05

3.2 Printed-Circuit Board Land Patterns

3.2.1 16-Pin SOIC

3.2.2 16-Pin DFN

NOTE: Because the metallic pad on the bottom of the

DFN package is connected to the substrate of the die,

Clare recommends that no printed circuit board traces

or vias be placed under this area to maintain minimum

creepage and clearance values.

3.3 Tape and Reel Packaging

3.3.1 16-Pin SOIC

2.00

(0.079)

1.27

(0.050)

(inches)

DIMENSIONS

9.40

(0.370)

0.60

(0.024)

DIMENSIONS

(inches)

5.80

(0.228)

0.35

(0.014)

1.05

(0.041)

0.80

(0.031)

NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2

Tape and Reel Packaging for 16-Pin SOIC Package

Dimensions

(inches)

Embossment

Embossed

Carrier

330.2 Dia

(13.00 Dia)

Top Cover

Tape Thickness

0.102 Max

(0.004 Max)

User Direction of Feed

Top Cover

Tape

P=12.00

(0.47)

0=10.90 + 0.15

(0.429 + 0.010)

0=10.70 + 0.15

(0.421 + 0.01)

W=16.00 + 0.30

(0.630 + 0.010)

0=3.20 + 0.15

(0.193 + 0.01)

1=2.70 + 0.15

(0.106 + 0.01)

Pin 1

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