ICS8735-21

700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR

2

ICS8735AM-21 REV. A JULY 31, 2008

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Name

Type

Description

CLK

Input

Pulldown

Non-inverting differential clock input.

nCLK

Input

Pullup

Inverting differential clock input.

nFB_IN

Input

Pullup

Inverting differential feedback input to phase detector for regenerating clocks with “zero delay.”

FB_IN

Input

Pulldown

Non-inverted differential feedback input to phase detector for regenerating clocks with

“zero delay.”

MR

Input

Pulldown

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true

output Q to go low and the inverted output nQ to go high. When logic LOW, the internal

dividers and the outputs are enabled. LVCMOS / LVTTL interface levels.

SEL0, SEL1,

SEL2, SEL3

Input

Pulldown

Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.

PLL_SEL

Input

Pullup

PLL select. Selects between the PLL and reference clock as the input to the dividers.

When LOW, selects reference clock. When HIGH, selects PLL.

LVCMOS/LVTTL interface levels.

nQ, Q

Output

Differential output pair. LVPECL interface levels.

nQFB, QFB

Output

Differential feedback output pair. LVPECL interface levels.

Power

Negative supply pin.

Power

Core supply pins.

Power

Analog supply pin.

Power

Output supply pin.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4

pF

Input Pullup Resistor

51

k

Ω

51

k

Ω