ATmega165-16AI datasheet(29/336 Pages) ATMEL

29 / 336 page

ATmega165/V

2573G–AVR–07/09

When applying an external clock, it is required to avoid sudden changes in the applied

clock frequency to ensure stable operation of the MCU. A variation in frequency of more

than 2% from one clock cycle to the next can lead to unpredictable behavior. It is

required to ensure that the MCU is kept in Reset during such changes in the clock

frequency.

Note that the System Clock Prescaler can be used to implement run-time changes of

the internal clock frequency while still ensuring stable operation. Refer to “System Clock

Prescaler” on page 29 for details.

Clock Output Buffer

When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This

mode is suitable when chip clock is used to drive other circuits on the system. The clock

will be output also during reset and the normal operation of I/O pin will be overridden

when the fuse is programmed. Any clock source, including internal RC Oscillator, can be

selected when CLKO serves as clock output. If the System Clock Prescaler is used, it is

the divided system clock that is output when the CKOUT Fuse is programmed.

Timer/Counter Oscillator

ATmega169 share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1

and XTAL2. This means that the Timer/Counter Oscillator can only be used when the

calibrated internal RC Oscillator is selected as system clock source. The Oscillator is

optimized for use with a 32.768 kHz watch crystal. See Figure 12 on page 25 for crystal

connection.

Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Reg-

ister is written to logic one. See “Asynchronous operation of the Timer/Counter” on page

134 for further description on selecting external clock as input instead of a 32 kHz

crystal.

System Clock Prescaler

The ATmega165 system clock can be divided by setting the Clock Prescale Register –

CLKPR. This feature can be used to decrease power consumption when the require-

ment for processing power is low. This can be used with all clock source options, and it

will affect the clock frequency of the CPU and all synchronous peripherals. clk

I/O, clkADC,

clk

CPU, and clkFLASH are divided by a factor as shown in Table 13.

Clock Prescale Register –

CLKPR

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The

CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to

Table 12. Start-up Times for the External Clock Selection

SUT1..0

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V

CC = 5.0V)

Recommended Usage

6 CK

14CK

BOD enabled

6 CK

14CK + 4.1 ms

Fast rising power

6 CK

14CK + 65 ms

Slowly rising power

Reserved

Bit

210

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

CLKPR

Read/Write

R/W

Initial Value

See Bit Description

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