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BQ20Z60-R1 Arkusz danych(PDF) 7 Page - Texas Instruments |
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BQ20Z60-R1 Arkusz danych(HTML) 7 Page - Texas Instruments |
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7 / 15 page ![]() SMBC SMBD SMBC SMBD SMBC SMBD S tSU(STA) S P tBUF tSU(STO) tR tF SMBC SMBD tTIMEOUT tHIGH tLOW tF tR tHD(DAT) tSU(DAT) tHD(STA) Start and Stop condition Wait and Hold condition Timeout condition Repeated Start condition bq20z60-R1 www.ti.com SLUS991 – DECEMBER 2009 SMBus TIMING SPECIFICATIONS (continued) VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tLOW:SEXT Cumulative clock low slave extend time See (3) 25 ms tLOW:MEXT Cumulative clock low master extend time See (4) 10 tF Clock/data fall time (VILMAX – 0.15 V) to (VIHMIN + 0.15 V) 300 ns tR Clock/data rise time 0.9 VCC to (VILMAX – 0.15 V) 1000 (3) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. (4) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop. SMBus TIMING DIAGRAM A. SCLKACK is the acknowledge related clock pulse generated by the master. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s) :bq20z60-R1 |
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