ADE7858ACPZ datasheet(69/76 Pages) AD

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Preliminary Technical Data

ADE7858

Rev. PrA | Page 69 of 76

Bit

Location

Bit

Mnemonic

Default

value

Description

If voltage channel compensation is necessary, these bits can vary only between 512 and 575.

If PHCALVAL bits are set with numbers between 384 and 511, the compensation behaves like

PHCALVAL set between 256 and 383.

If PHCALVAL bits are set with numbers between 512 and 1023, the compensation behaves like

PHCALVAL bits set between 384 and 511.

15-10

Reserved

000000

Reserved. These bits do not manage any functionality.

Table 38. PHSIGN register (address 0xE617)

Bit

Location

Bit

Mnemonic

Default

value

Description

AWSIGN

-0: if the total active power on phase A is positive.

-1: if the total active power on phase A is negative.

BWSIGN

-0: if the total active power on phase B is positive.

-1: if the total active power on phase B is negative.

CWSIGN

-0: if the total active power on phase C is positive.

-1: if the total active power on phase is negative.

SUM1SIGN

-0: if the sum of all phase powers in the CF1 data path is positive.

-1: if the sum of all phase powers in the CF1 data path is negative.

Phase powers in the CF1 data path are identified by bits 2,1,0 (TERMSEL1) of COMPMODE[15:0]

AVARSIGN

-0: if the reactive power identified by bit 7 (REVRPSEL) bit in ACCMODE[7:0] register (total of

fundamental) on phase A is positive.

-1: if the total reactive power on phase A is negative.

BVARSIGN

-0: if the total reactive power on phase B is positive.

-1: if the total reactive power on phase B is negative.

CVARSIGN

-0: if the total reactive power on phase C is positive.

-1: if the total reactive power on phase C is negative.

SUM2SIGN

-0: if the sum of all phase powers in the CF2 data path is positive.

-1: if the sum of all phase powers in the CF2 data path is negative.

Phase powers in the CF2 data path are identified by bits 5,4,3 (TERMSEL2) of COMPMODE[15:0]

SUM3SIGN

-0: if the sum of all phase powers in the CF3 data path is positive.

-1: if the sum of all phase powers in the CF3 data path is negative.

Phase powers in the CF3 data path are identified by bits 8,7,6 (TERMSEL3) of COMPMODE[15:0]

15-9

Reserved

000 0000

Reserved . These bits are always 0.

Table 39. CONFIG register (address 0xE618)

Bit

Location

Bit

Mnemonic

Default

value

Description

INTEN

Integrator Enable. When this bit is set to 1, the internal digital integrator is enabled for use in

meters utilizing Rogowski Coils on all 3 phase and neutral current inputs. When this bit is cleared

to 0, the internal digital integrator is disabled.

2,1

Reserved

Reserved. These bits do not manage any functionality.

SWAP

When this bit is set to 1, the voltage channel outputs are swapped with the current channel

outputs. Thus, the current channel information will be present in the voltage channel registers

and vice versa.

MOD1SHORT

When this bit is set to 1, the voltage channel ADCs behave as if the voltage inputs were put to

ground.

MOD2SHORT

When this bit is set to 1, the current channel ADCs behave as if the voltage inputs were put to

ground.

HSDCEN

When this bit is set to 1, the HSDC serial port is enabled and HSCLK functionality is chosen at

CF3/HSCLK pin. When this bit is cleared to 0, HSDC is disabled and CF3 functionality is chosen at

CF3/HSCLK pin.

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