MPC5123 datasheet(34/86 Pages) FREESCALE

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MPC5121E/MPC5123 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

Figure 9 and Figure 10 shows the DDR SDRAM read timing

Figure 9. DDR Read Timing, DQ vs DQS

Figure 10. DDR Read Timing, DQSEN

Figure 11 provides the AC test load for the DDR bus.

Figure 11. DDR AC Test Load

3.3.6

PCI

The PCI interface on the MPC5121e/MPC5123 is designed to PCI Version 2.3 and supports 33 and 66 MHz PCI operations.

See the PCI Local Bus Specification; the component section specifies the electrical and timing parameters for PCI components

with the intent that components connect directly together whether on the planar or an expansion board, without any external

buffers or other glue logic. Parameters apply at the package pins, not at expansion board edge connectors.

The PCI_CLK is used as output clock, the MPC5121e/MPC5123 is a PCI host device only.

Figure 12 shows the clock waveform and required measurement points for 3.3 V signaling environments. Table 21 summarizes

the clock specifications.

DQS(in)

Any DQ(in)

tDQSQ

MCK

DQS (in)

tOS

tOH

Command

Address

Read

tDQSEN (min)

tDQSEN

Output

Z0 =50 Ω

RL = 50 Ω

VDD_MEM_IO/2

MPC5123 Arkusz danych(PDF) 34 Page - Freescale Semiconductor, Inc