AS3524 datasheet(97/124 Pages) AMSCO

97 / 124 page

AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

Table 23 PLLA Supervisor Register

Name

Base

Default

CGU_PLLASUP

AS3525_CGU_BASE

0x08

PLLA Supervisor Register

Offset0x08

This register contains control bits of the PLLA which are used very rarely, but have

major impact on the functionality of the system.

Bit

Bit Name

Default

Access

Bit Description

PLLA_PD

0x00

R/W

PLLA power down if SET

PLLA_OEB

0x00

R/W

PLLA output enable, active low

PLLA_BP

0x00

R/W

PLLA bypass if SET

PLLA_FIN_SEL

0x00

R/W

PLLA clock source select

0: clk_int [PAD]

1: clk_ext [PAD]

Table 24 PLBB Supervisor Register

Name

Base

Default

CGU_PLLBSUP

AS3525_CGU_BASE

0x08

PLLB Supervisor Register

Offset0x0c

This register contains control bits of the PLLB which are used very rarely, but have

major impact on the functionality of the system.

Bit

Bit Name

Default

Access

Bit Description

PLLB_PD

0x00

R/W

PLLB power down if SET

PLLB_OEB

0x00

R/W

PLLB output enable, active low

PLLB_BP

0x00

R/W

PLLB bypass if SET

PLLB_FIN_SEL

0x00

R/W

PLLB clock source select

0: clk_int [PAD]

1: clk_ext [PAD]

Table 25 Processor Clock Controller Register

Name

Base

Default

CGU_PROC

AS3525_CGU_BASE

0x00

Processor Clock Controller Register

Offset0x10

This register contains control bits for ARM processor clock generation => FCLK.

Bit

Bit Name

Default

Access

Bit Description

7:4

FCLK_POSTDIV_SEL

[3:0]

0x00

R/W

post divider division ratio => post_div =

1/(fclk_postdiv_sel + 1)

3:2

FCLK_PREDIV_SEL

[1:0]

0x00

R/W

pre divider (fractional) division ratio

00: pre_div = 1/1

01: pre_div = 7/8

10: pre_div = 6/8

11: pre_div = 5/8

1:0

FCLK_SEL[1:0]

0x00

R/W

clkin select

00: clk_main

01: plla_fout

10: pllb_fout

11: reserved (clk_main)

NOTE: f(fclk) := f(clkin) * pred_div * post_div;

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