PAS5101CS Specification

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission

.

2

PixArt Imaging Inc.

v1.0 2005/4/27

1.

Pin Assignment

Figure 1.1 Shows the PAS5101CS pin diagram

Pin No.

Name

Type

Description

E4

VSSA

GND

Analog ground.

D4

VDDA

PWR

Analog power, 2.5V

E5

PWDN

IN

Power Down (chip power down if high ).

D5

VREF

IN

Internal voltage reference.

C5

VDDD

PWR

Nc, Internal Regulator 1.8V.

B5

VSYNC

OUT

Vertical synchronization signal.

A5

HSYNC

OUT

Horizontal synchronization signal.

B4

PXCLK

OUT

Pixel clock output.

A4

VDDQ

PWR

Sensor VDD, 2.5V ~ 3.3V.

B3

SYSCLK

IN

System clock input.

A3

RESET

IN

Resets all registers to their default values ( chip reset if high .)

B2

VSSD

GND

Digital ground.

A2

PX9

OUT

Digital data out.

B1

PX8

OUT

Digital data out.

A1

PX7

OUT

Digital data out.

C1

PX6

OUT

Digital data out.

D1

PX5

OUT

Digital data out.

E1

PX4

OUT

Digital data out.

D2

PX3

OUT

Digital data out.

E2

PX2

OUT

Digital data out.

C4

PX1

OUT

Digital data out.