Power-Fail Comparator

The power-fail comparator can be used for various pur-

poses because its output and noninverting input are

not internally connected. The inverting input is internal-

ly connected to a 1.25V reference.

To build an early-warning circuit for power failure, con-

nect the PFI pin to a voltage divider (see

Typical

Operating Circuit). Choose the voltage divider ratio so

that the voltage at PFI falls below 1.25V just before the

+5V regulator drops out. Use PFO to interrupt the µP

so it can prepare for an orderly power-down.

__________Applications Information

Ensuring a Valid RESET

output no longer sinks current—it becomes an open cir-

cuit. High-impedance CMOS logic inputs can drift to

undetermined voltages if left undriven. If a pull-down

resistor is added to the RESET pin as shown in Figure 5,

any stray charge or leakage currents will be drained to

ground, holding RESET low. Resistor value (R1) is not

critical. It should be about 100k

Ω, large enough not to

load RESET and small enough to pull RESET to ground.

Monitoring Voltages Other Than the

Unregulated DC Input

Monitor voltages other than the unregulated DC by

connecting a voltage divider to PFI and adjusting the

ratio appropriately. If required, add hysteresis by con-

necting a resistor (with a value approximately 10 times

the sum of the two resistors in the potential divider net-

work) between PFI and PFO. A capacitor between PFI

and GND will reduce the power-fail circuit’s sensitivity

to high-frequency noise on the line being monitored.

RESET can be asserted on other voltages in addition to

pulse when PFI drops below 1.25V. Figure 6 shows the

MAX705-MAX708 configured to assert RESET when the

+5V supply falls below the reset threshold, or when the

+12V supply falls below approximately 11V.

Monitoring a Negative Voltage

The power-fail comparator can also monitor a negative

supply rail (Figure 7). When the negative rail is good (a

negative voltage of large magnitude), PFO is low, and

when the negative rail is degraded (a negative voltage

of lesser magnitude), PFO is high. By adding the resis-

tors and transistor as shown, a high PFO triggers reset.

As long as PFO remains high, the MAX705-

MAX708/MAX813L will keep reset asserted (RESET =

low, RESET = high). Note that this circuit’s accuracy

and the resistors.

Low-Cost, µP Supervisory Circuits

_______________________________________________________________________________________

7

+5V

0V

WDI

+5V

0V

WDO

+5V

0V

RESET

+5V

0V

(RESET)

( ) ARE FOR MAX813L ONLY.

RESET EXTERNALLY

TRIGGERED BY MR

Figure 3. MAX705/MAX706/MAX813L Watchdog Timing

Figure 4. MAX705/MAX706 RESET, MR, and WDO Timing with

WDI Three-Stated. The MAX707/MAX708/MAX813L RESET

output is the inverse of RESET shown.

+5V

0V

RESET

WDO

+5V

0V

MR

MR EXTERNALLY DRIVEN LOW

+5V

0V