WM8181

Advanced Information

WOLFSON MICROELECTRONICS LTD

AI Rev 3.0 January 2000

2

PIN CONFIGURATION

ORDERING INFORMATION

DEVICE

TEMP. RANGE

PACKAGE

XWM8181CDW

0 to 70

16-pin SOIC wide

body

DVDD

AGND2

215

AVDD

AGND1

116

DOUT

VREFIN

314

MCLK

VINP

413

VSMP

VINM

512

CLAMP

VRB

611

DGND

VRT

710

9

8

NC

NC

PIN DESCRIPTION

PIN

NAME

TYPE

DESCRIPTION

1

AGND1

Ground

General analogue ground (0V).

2

AGND2

Ground

Reference analogue ground (0V).

3

VREFIN

Analogue input

Allows external control of the ADC references.

4

VINP

Analogue input

Positive video input

5

VINM

Analogue input

Negative video input

Usually one of VINP or VINM will be an externally

applied d.c. bias, the other will be a signal voltage.

6

VRB

Analogue output

Lower reference voltage. This pin must be connected to AGND and VRT via

decoupling capacitors. See Recommended External Components section for details.

7

VRT

Analogue output

Upper reference voltage. This pin must be connected to AGND and VRB via

decoupling capacitors. See Recommended External Components section for details.

8NC

No internal connection

9NC

No internal connection

10

DGND

Ground

Digital ground (0V).

11

CLAMP

Digital input

Connects VINP and VINM together, active high.

12

VSMP

Digital input

Video sample synchronisation pulse, at input pixel rate. Sampled on rising edge of

MCLK. See Operational Timing Diagrams for details.

13

MCLK

Digital input

Master clock. This clock can be applied at either 12 or 16 times the input pixel rate.

14

DOUT

Digital output

ADC serial data output, changes on falling edge of MCLK.

15

DVDD

Supply

Digital supply (3.3V, 5V).

16

AVDD

Supply

Analogue supply (3.3V, 5V).

POSSIBLE POWER SUPPLY COMBINATIONS

COMBINATION

AVDD (VOLTS)

DVDD (VOLTS)

155

23.3

3.3

35

3.3