X68C64

5

cycle is complete, the toggling will cease and the device

will be accessible for additional read or write operations.

Due to the dual plane architecture, reads for polling must

occur in the plane that is being written; that is, the state

Toggle Bit Polling.

Toggle Bit Polling

Because the X68C64 typical nonvolatile write cycle time

is less than the specified 5ms, Toggle Bit Polling has

been provided to determine the early completion of

toggle from HIGH to LOW and LOW to HIGH on subse-

quent attempts to read the device. When the internal

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

Toggle Bit Polling E Control

3868 FHD F08

CE

AS

A/D0–A/D7

A8–A12

E

R/W

AIN

DIN

A12=n

OPERATION

LAST BYTE

WRITTEN

I/O6=X

X68C64 READY FOR

NEXT OPERATION

AIN DOUT

A12=n

AIN DOUT

A12=n

AIN DOUT

A12=n

AIN

A12=n

AIN

ADDR

I/O6=X

I/O6=X

I/O6=X

DOUT