AD9553SLASHPCBZ datasheet(23/44 Pages) AD

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AD9553

Rev. 0 | Page 23 of 44

Table 19. Output Mode Control Bits

Mode Control

Bits

Logic

Family

Pin Function of the Output

Driver

000

CMOS

Both pins active

001

CMOS

Positive pin active, negative

pin tristate

010

CMOS

Positive pin tristate, negative

pin active

011

CMOS

Both pins tristate

100

LVDS

Both pins active

101

LVPECL

Both pins active

110

Unused

111

Unused

Note that the pin decoder for the OM[2:0] pins generates two

sets of mode control bits: one set for the OUT1 driver and

another set for the OUT2 driver. The relationship between the

logic levels applied to the OM[2:0] pins and the resulting mode

control bits appears in Table 20.

Table 20. OM[2:0] Pin Decoder

Pins OM[2:0]

Mode Control Bits

OUT1

OUT2

000

101

001

101

100

010

100

101

011

101

001

100

101

100

001

110

001

100

111

001

This decoding scheme allows the OM[2:0] pins to establish a

matrix of logic family selections for the OUT1 and OUT2 drivers

as shown in Table 21. Note that when the OM[2:0] pins select the

CMOS logic family, only the positive pin active, negative pin tristate

output driver pin function option is available.

Table 21. Logic Family Assignment via the OM[2:0] Pins

Pins OM[2:0]

Logic Family

OUT1

OUT2

000

LVPECL

001

LVPECL

LVDS

010

LVDS

LVPECL

011

LVPECL

CMOS

100

LVDS

101

LVDS

CMOS

110

CMOS

LVDS

111

CMOS

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