CS4297 datasheet(44/81 Pages) CIRRUS

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CS4205

DS489PP4

5.26

Misc. Crystal Control Register (Index 60h)

DPC

DAC Phase Control. This bit controls the phase of the PCM stream sent to the DACs (after

SRC). When ‘cleared’ the phase of the signal will remain unchanged. When this bit is ‘set’,

each PCM sample will be inverted before being sent to the DACs.

10dB

Microphone 10 dB Boost. When ‘set’, the 10dB bit enables an additional boost of 10 dB on

the selected microphone input. In combination with the 20dB boost bit in the Microphone Vol-

ume Register (Index 0Eh) this bit allows for variable boost from 0 dB to +30 dB in steps of

10 dB.

CRST

Force Cold Reset. The CRST bit is used as an override to the New Warm Reset behavior

defined during PR4 powerdown. If this bit is ‘set’, an active RESET# signal will force a Cold

Reset to the CS4205 during a PR4 powerdown.

GPOC

General Purpose Output Control. The GPOC bit specifies the mechanism by which the status

of a General Purpose Output pin can be controlled. If this bit is ‘cleared’, the GPO status is

controlled through the standard AC ’97 method of setting the appropriate bits in output

Slot 12. If this bit is ‘set’, the GPO status is controlled through the GPIO Pin Status Register

(Index 54h).

LOSM

Loss of SYNC Mute Enable. The LOSM bit controls the loss of SYNC mute function. If this bit

is ‘set’, the CS4205 will mute all analog outputs for the duration of loss of SYNC. If this bit is

‘cleared’, the mixer will continue to function normally during loss of SYNC. The CS4205 ex-

pects to sample SYNC ‘high’ for 16 consecutive BIT_CLK periods and then ‘low’ for 240 con-

secutive BIT_CLK periods, otherwise loss of SYNC becomes true.

Default

0003h

D15

D14

D13

D12

D11

D10

Res

DPC

Reserved

10dB

CRST

Reserved

GPOC

Reserved

LOSM

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