CS4294SLASHCS4298 datasheet(33/81 Pages) CIRRUS

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CS4205

DS489PP4

5.10

Record Gain Register (Index 1Ch)

Mute

Record Gain Mute. Setting this bit mutes the input to the L/R ADCs.

GL[3:0]

Left ADC Gain. The GL[3:0] bits control the input gain on the left channel of the analog

source, applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB

gain adjustment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain. See Table 10 for

further details.

GR[3:0]

Right ADC Gain. The GR[3:0] bits control the input gain on the right channel of the analog

source, applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB

gain adjustment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain. See Table 10 for

further details.

Default

8000h. This value corresponds to 0 dB gain and Mute ‘set’.

5.11

Record Gain Mic Register (Index 1Eh)

Mute

Mic Record Gain Mute. When ‘set’, mutes the input to the microphone ADC.

GM[3:0]

Mic ADC gain. The GM[3:0] bits control the input gain on the microphone source. The gain is

applied after the input mux and before the ADC. Each step corresponds to 1.5 dB gain ad-

justment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain. See Table 10 for further

details.

Default

8000h. This value corresponds to 0 dB gain and Mute ‘set’.

D15

D14

D13

D12

D11

D10

Mute

000

GL3

GL2

GL1

GL0

0000

GR3

GR2

GR1

GR0

Gx3 - Gx0 Gain Level

1111

+22.5 dB

……

0001

+1.5 dB

0000

0 dB

Table 10. Record Gain Values

D15

D14

D13

D12

D11

D10

Mute

00000000000

GM3

GM2

GM1

GM0

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