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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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XIO2001 Arkusz danych(PDF) 17 Page - Texas Instruments |
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XIO2001 Arkusz danych(HTML) 17 Page - Texas Instruments |
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17 / 128 page  XIO2001 www.ti.com SCPS212D – MAY 2009 – REVISED JANUARY 2010 Table 2-4. PCI Express Terminals (continued) ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL SIGNAL DESCRIPTION BALL # BALL # PIN # TYPE TYPE RAIL PARTS REFCLK+ C13 C13 93 DI HS DIFF VDD_33 Reference clock. REFCLK+ and REFCLK– IN comprise the differential input pair for the – 100-MHz system reference clock. For a single-ended, 125-MHz system reference clock, use the REFCLK+ input. REFCLK– C12 B13 94 DI HS DIFF VDD_33 Reference clock. REFCLK+ and REFCLK– Capacitor IN comprise the differential input pair for the for VSS for 100-MHz system reference clock. For a single- single-ended, 125-MHz system reference clock, ended node attach a capacitor from REFCLK– to VSS. REF0_PCIE K12 M13 71 I/O BIAS – External reference resistor + and – terminals for REF1_PCIE K13 L13 72 setting TX driver current. An external resistance of 14,532- Ω is connected between REF0_PCIE External and REF1_PCIE terminals. To eliminate the need resistor for a custom resistor, two series resistors are recommended: a 14.3-k Ω, 1% resistor and a 232- Ω, 1% resistor. RXP E13 E13 87 DI HS DIFF VSS High-speed receive pair. RXP and RXN comprise RXN E12 D13 88 IN – the differential receive pair for the single PCI Express lane supported. TXP G13 H13 80 DO HS DIFF VDD_15 High-speed transmit pair. TXP and TXN comprise Series TXN G12 G13 81 OUT the differential transmit pair for the single PCI capacitor Express lane supported. WAKE M13 L12 68 O LV VDD_33_ Wake is an active low signal that is driven low to CMOS COMBIO reactivate the PCI Express link hierarchy’s main power rails and reference clocks. – Note: Since WAKE is an open-drain output buffer, a system side pullup resistor is required. Table 2-5. PCI System Terminals ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL SIGNAL DESCRIPTION BALL # BALL # PIN # TYPE TYPE RAIL PARTS AD31 N05 N05 44 I/O PCI PCIR PCI address data lines AD30 N04 L05 43 Bus AD29 L05 M05 42 AD28 M05 N04 41 AD27 N03 N03 40 AD26 M04 L04 39 AD25 N02 M04 38 AD24 M03 N02 37 AD23 L04 L03 35 AD22 M02 M02 34 AD21 L03 N01 32 AD20 M01 L02 31 AD19 L02 K02 30 AD18 L01 M01 29 AD17 K02 K03 28 AD16 K01 L01 26 – AD15 E01 F02 12 AD14 E02 E03 11 AD13 E03 E01 10 AD12 D01 E02 9 AD11 D02 D01 8 AD10 C01 C01 6 AD9 C02 D02 5 AD8 D03 B01 4 AD7 C03 A01 1 AD6 B02 B03 128 AD5 C04 C03 127 AD4 A02 A02 125 AD3 B03 A03 124 AD2 B04 C04 123 AD1 A03 C05 122 AD0 C05 B04 121 Copyright © 2009–2010, Texas Instruments Incorporated Overview 17 Submit Documentation Feedback Product Folder Link(s): XIO2001 |
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