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PCIMX258CJM4A Arkusz danych(PDF) 53 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Arkusz danych(HTML) 53 Page - Freescale Semiconductor, Inc |
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53 / 144 page ![]() i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 Freescale Semiconductor 53 Figure 21. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge Table 39. CSI Gated Clock Mode Timing Parameters ID Parameter Symbol Min. Max. Units P1 CSI VSYNC to HSYNC time tV2H 67.5 — ns P2 CSI HSYNC setup time tHsu 1 — ns P3 CSI DATA setup time tDsu 1 — ns P4 CSI DATA hold time tDh 1.2 — ns P5 CSI pixel clock high time tCLKh 10 — ns P6 CSI pixel clock low time tCLKl 10 — ns P7 CSI pixel clock frequency fCLK — 48 ± 10% MHz PIXCLK VSYNC DATA[15:0] P6 P1 P3 P4 HSYNC P2 P5 P7 |
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