PCA9532_4

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 17 March 2009

18 of 29

NXP Semiconductors

PCA9532

11. Dynamic characteristics

[1]

[2]

[3]

[4]

Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.

[5]

Table 14.

Dynamic characteristics

Symbol

Parameter

Conditions

Standard-mode

Unit

Min

Max

Min

Max

SCL clock frequency

0

100

0

400

kHz

bus free time between a STOP and

START condition

4.7

-

1.3

-

µs

hold time (repeated) START condition

4.0

-

0.6

-

µs

set-up time for a repeated START

condition

4.7

-

0.6

-

µs

set-up time for STOP condition

4.0

-

0.6

-

µs

data hold time

0

-

0

-

ns

data valid acknowledge time

[1]

-

600

-

600

ns

data valid time

LOW-level

[2]

-

600

-

600

ns

HIGH-level

[2]

-

1500

-

600

ns

data set-up time

250

-

100

-

ns

LOW period of the SCL clock

4.7

-

1.3

-

µs

HIGH period of the SCL clock

4.0

-

0.6

-

µs

rise time of both SDA and SCL signals

-

1000

300

ns

fall time of both SDA and SCL signals

-

300

300

ns

pulse width of spikes that must be

suppressed by the input filter

-

50

-

50

ns

Port timing

data output valid time

-

200

-

200

ns

data input set-up time

100

-

100

-

ns

data input hold time

1

-

1

-

µs

Reset

reset pulse width

10

-

10

-

ns

reset recovery time

0

-

0

-

ns

reset time

[4][5]

400

-

400

-

ns