SMP402 datasheet(3/16 Pages) POWERINT

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SMP402

Pin Functional Description

Pin 1:

IN is

the high-voltage input to the

switching regulator. This is the Source

connection of the P-Channel power

MOSFET pass transistor.

Pin 2:

LS is an internal supply for the level

shift circuit that drives the P-Channel

MOSFET. A capacitor should be placed

between V

LS and VIN for bypassing. VLS

is normally 10 V below V

IN.

Pin 3:

The power supply can be shut down by

pulling ENABLE low.

Pin 4:

D GND is the common return point for

the power and logic portions of the

circuit.

Pin 5:

A GND is the common return point.

EXT and CEXT are directly connected to

this point.

Pin 6:

The SENSE+ input monitors the polarity

and level of the input voltage through an

external resistor for ISDN emergency

standby sensing.

Pin 7:

The SENSE- input monitors the polarity

and level of the input voltage through an

external resistor for ISDN emergency

standby sensing.

Pin 8:

A 20.5 k

Ω resistor connected between

EXT and A GND sets the internal bias

currents including oscillator charge and

discharge currents.

Pin 9:

The oscillator frequency can be

programmed by selecting the value of

the capacitor connected between C

EXT

and A GND.

Pin 10:

BIAS can be connected to the output 5 V

rail of the converter to reduce power

dissipation. The internal 5 V regulator is

cut off when the output is in regulation.

Pin 11:

EA OUT is the error amplifier output

pin for connection to the external

compensation network.

Pin 12:

EA IN is the error amplifier negative

input for connection to the feedback and

compensation networks.

Pin 13:

S is the internal supply voltage. This

pin is brought out for external bypassing.

Pin 14:

The LEVEL output indicates when the

input voltage is in its normal operating

range.

Pin 15:

The POLARITY output is used to notify

a microprocessor of an emergency

standby condition for ISDN applications.

Pin 16:

OUT is the Drain connection of the P-

Channel pass transistor.

Functional Description

High Voltage Regulator

The high-voltage regulator provides the

bias current required by the controller

and driver circuitry. The pre-regulator

consists of a high voltage MOSFET, a

gate bias current source, and an error

amplifier. The error amplifier regulates

S to approximately 5 V by controlling

the gate of the MOSFET.

In 5 V output applications, the control

circuitry may also be operated by

connecting the V

BIAS pin to the output 5

V rail of the converter to reduce power

dissipation. The internal 5 V regulator is

cut off automatically when the converter

output is in regulation. Only the supply

current for the level shift stage (

≈50 µA)

and the AC switching currents for the P-

Channel output device are drawn from

the V

IN supply under this condition.

unused, V

BIAS must be hardwired to A

GND to disable the automatic switchover

during power-up.

LS is the level-shift supply for driving

the gate of the internal P-channel

MOSFET.

The voltage at V

approximately 10 V below V

IN. VS is the

supply voltage for the controller and

driver circuitry.

External bypass

capacitors connected to V

LS and VS are

required for filtering and reducing noise.

UV Lockout

During power-up, the undervoltage

lockout circuit keeps the P-channel

output transistor in the off state until the

internal V

S supply is in regulation and

the voltage sensed by the input monitor

circuit is within the normal operation

range (>12 V).

Band Gap Reference

REF is the 1.3 V reference voltage

generated

the

temperature-

compensated bandgap reference and

buffer. This voltage is used for setting

thresholds for the error amplifier and

over temperature circuit.

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