ADT7490ARQZ-R7 datasheet(72/75 Pages) ONSEMI

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Table 84. Register 0x8F — Dynamic TMIN Control Register 2 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W (Note 1)

Description

[2:0]

CYR1

R/W

3−Bit Remote 1 Cycle Value. These three bits define the delay time between making

subsequent TMIN adjustments in the control loop for the Remote 1 channel in terms of

number of monitoring cycles. The system has associated thermal time constants that need to

be found to optimize the response of fans and the control loop.

Bit Code

Decrease Cycle

Increase Cycle

000

001

010

011

100

101

110

111

8 cycles (1 sec)

16 cycles (2 sec)

32 cycles (4 sec)

64 cycles (8 sec)

128 cycles (16 sec)

256 cycles (32 sec)

512 cycles (64 sec)

1024 cycles (128 sec)

16 cycles (2 sec)

32 cycles (4 sec)

64 cycles (8 sec)

128 cycles (16 sec)

256 cycles (32 sec)

512 cycles (64 sec)

1024 cycles (128 sec)

2048 cycles (256 sec)

[5:3]

CYL

R/W

3−Bit Local Temperature Cycle Value. These three bits define the delay time between making

subsequent TMIN adjustments in the control loop for the local temperature channel in terms of

number of monitoring cycles. The system has associated thermal time constants that need to

be found to optimize the response of fans and the control loop.

Bit Code

Decrease Cycle

Increase Cycle

000

001

010

011

100

101

110

111

8 cycles (1 sec)

16 cycles (2 sec)

32 cycles (4 sec)

64 cycles (8 sec)

128 cycles (16 sec)

256 cycles (32 sec)

512 cycles (64 sec)

1024 cycles (128 sec)

16 cycles (2 sec)

32 cycles (4 sec)

64 cycles (8 sec)

128 cycles (16 sec)

256 cycles (32 sec)

512 cycles (64 sec)

1024 cycles (128 sec)

2048 cycles (256 sec)

[7:6]

CYR2

R/W

2 LSBs of 3−Bit Remote 2 Cycle Value. The MSB of the 3−bit code resides in the Dynamic

TMIN Control Register 1 (Register 0x8E). These three bits define the delay time between

making subsequent TMIN adjustments in the control loop for the Remote 2 channel in terms

of number of monitoring cycles. The system has associated thermal time constants that need

to be found to optimize the response of fans and the control loop.

Bit Code

Decrease Cycle

Increase Cycle

000

001

010

011

100

101

110

111

8 cycles (1 sec)

16 cycles (2 sec)

32 cycles (4 sec)

64 cycles (8 sec)

128 cycles (16 sec)

256 cycles (32 sec)

512 cycles (64 sec)

1024 cycles (128 sec)

16 cycles (2 sec)

32 cycles (4 sec)

64 cycles (8 sec)

128 cycles (16 sec)

256 cycles (32 sec)

512 cycles (64 sec)

1024 cycles (128 sec)

2048 cycles (256 sec)

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this

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