SC174 datasheet(14/27 Pages) SEMTECH

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Figure 7 — Valley Current Limit

Setting the valley current limit to a value of I

LIM results

in a peak inductor current of ILIM plus the peak-to-peak

ripple current. In this situation, the average (load) current

through the inductor will be I

LIM plus one half the peak-

to-peak ripple current.

Soft start of PWM Regulator

Soft start is achieved in the PWM regulator by using

an internal voltage ramp as the reference for the FB

comparator. The voltage ramp is generated using an

internal charge pump which drives the reference from

zero to 750mV in ~1.8mV increments, using an internal

~500kHz oscillator. When the ramp voltage reaches

750mV, the ramp is ignored and the FB comparator

switches over to a fixed 750mV threshold. During soft start

the output voltage tracks the internal ramp, which limits

the start-up inrush current and provides a controlled soft

start profile for a wide range of applications. Typical soft

start ramp time is 0.85ms.

Applications Information (continued)

Time

IPEAK

ILOAD

ILIM

During soft start the regulator turns off the low-side

MOSFET on any cycle if the inductor current falls to zero.

This prevents negative inductor current, allowing the

device to start into a pre-biased output. This soft start

operation is implemented even if FCM is selected. FCM

operation is allowed only after PGOOD is high.

Power Good Output

The power good (PGOOD) output is an open-drain output

which requires a pull-up resistor. When the output volt-

age is 10% below the nominal voltage, PGOOD is pulled

low. It is held low until the output voltage returns to the

nominal voltage. PGOOD is held low during soft start and

activated approximately 1ms after V

OUT reaches regula-

tion. The total PGOOD delay is typically 2ms.

PGOOD will transition low if the V

FB pin exceeds +20% of

nominal, which is also the over-voltage shutdown thresh-

old (900mV). PGOOD also pulls low if the EN/PSV pin is

low when VDD is present.

Output Over-Voltage Protection

Over-Voltage Protection (OVP) becomes active as soon

as the device is enabled. The threshold is set at 750mV +

20% (900mV). When V

FB exceeds the OVP threshold, DL

latches high and the low-side MOSFET is turned on. DL

remains high and the controller remains off, until the EN/

PSV input is toggled or VDD is cycled. There is a 5μs delay

built into the OVP detector to prevent false transitions.

PGOOD is also low after an OVP event.

Output Under-Voltage Protection

When V

FB falls to 75% of its nominal voltage (falls to

562.5mV) for eight consecutive clock cycles, the switcher

is shut off and the DH and DL drives are pulled low to turn

off the MOSFETs. The controller stays off until EN/PSV is

toggled or VDD is cycled.

VDD UVLO, and POR

Under-Voltage Lock-Out (UVLO) circuitry inhibits switch-

ing and tri-states the power FETs until VDD rises above

2.9V. An internal Power-On Reset (POR) occurs when

VDD exceeds 2.9V, which resets the fault latch and soft

start counter to begin the soft start cycle. The SC174 then

begins a soft start cycle. The PWM will shut off if VDD falls

SC174

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