SAN3010

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Since only one row/column is forced high or low at the same time the number of µC output port pins can be limited

by using a 1-of-8 decoder (74HC138). The 3 bits (A,B,C, respectively Port1 pins 0..2) select the appropriate

row/column, Port 1.4 disables all outputs.

The selected row/column is forced high or low depending on the state of Port1.5 .

Port 1.7 is used as input to detect the acknowledge of the SA253x during the scanning phase. Acknowledge is

done by the rising edge of either C1,C2,C3 or C4.

The detection logic can be simplified by just monitoring C1 and C2, because one of both can always be used for

detection (see table 1, ColY).

Diode D1 is necessary to prevent collision of two outputs when Port1 is in output mode. Since Port1 of the 80C31 is

an open-drain output a diode can be used. For other controllers, using standard I/O, a resistor must be used in

place of the diode.

See also: Appendix B:

The interfacing procedure is shown in the attached flowchart, additional information is given below:

1) Key entry can only occur, when the SA253x has been off-hook for >20ms.

2) Internal key scanning of the SA253x is started when any Row (in our case: R1) has been forced low, then the

acknowledge by the SA253x is done by moving specific col-pins high.

3) When this Lo/Hi transition is detected by the

µC the asynchronous timing must be started.

4) SCAN1 and SCAN 2 are the time slots at which a certain row must be forced high (SCAN1) and forced low

(SCAN 2 ) , at time slot SCAN3 a certain column must be forced high. The key entry corresponding Row and

Column is shown in table 1. Between the SCAN1..3 time slots all rows and columns must be high ohmic (see

flowchart).

5) a valid key entry is accepted, when the SCAN1..3 procedure has been repeated 9 times.

6) a certain constant delay must be added between key entries. The only exception is, when memory keys are

cascaded. In this special case, entering a subsequent memory key is only accepted, when the previous memory

has been fully dialed out.

See also: Appendix C:

Attached is a sample software program, written in 8051 Assembler language which incorporates all the necessary

timing and correct row/column selection. The only entry is to load the accumulator with a key code and then make a

subroutine call.

See Table 1 for appropriate key codes when using either SA2531-2

The assembler command lines are well described, so it should be easily understood.

Again, adaption to other controllers based upon this software should be no problem.

Care must be taken when using a different system clock speed. In this case the delay blocks must be recalculated

based on the number of machine cycles used.

8 Scanning table/flowchart

9 Sample software