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KM418RD8ACD-RK80 Arkusz danych(PDF) 54 Page - Samsung semiconductor |
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KM418RD8ACD-RK80 Arkusz danych(HTML) 54 Page - Samsung semiconductor |
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54 / 64 page  Page 51 KM416RD8AC(D)/KM418RD8AC(D) Direct RDRAM™ Rev. 1.01 Oct. 1999 The SCK clock is also used for sampling data on RSL inputs in one situation. Figure 48 shows the PDN and NAP exit sequences. If the PSX field of the INIT register is one (see Figure 27), then the PDN and NAP exit sequences are broad- cast; i.e. all RDRAMs that are in PDN or NAP will perform the exit sequence. If the PSX field of the INIT register is zero, then the PDN and NAP exit sequences are directed; i.e. only one RDRAM that is in PDN or NAP will perform the exit sequence. The address of that RDRAM is specified on the DQA[5:0] bus in the set/hold window tS3/tH3 around the rising edge of SCK. This is shown in Figure 57. The SCK timing point is measured at the 50% level, and the DQA[5:0] bus signals are measured at the VREF level. Figure 57: CMOS Timing - Device Address for NAP or PDN Exit VIH,CMOS 50% VIL,CMOS 80% 20% SCK VDIH VREF VDIL 80% 20% DQA[5:0] tS3 tH3 PDEV |
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