2

0735U–PLD–7/10

Atmel ATF22V10C(Q)

Figure 1-1.

Logic Diagram

2.

Pin Configurations

Table 2-1.

Pin Configurations (All Pinouts Top View)

Pin Name

Function

CLK

Clock

IN

Logic Inputs

I/O

Bi-directional Buffers

GND

Ground

VCC

+5V Supply

PD

Power-down

Figure 2-1.

TSSOP

Figure 2-2.

DIP/SOIC

Figure 2-3.

PLCC/LCC

Note:

For all PLCCs (except “-5”), pins 1, 8, 15 and 22 can be left unconnected. However, if they are

connected, superior performance will be achieved

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

CLK/IN

IN

IN

IN/PD

IN

IN

IN

IN

IN

IN

IN

GND

VCC

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

IN

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

CLK/IN

IN

IN

IN/PD

IN

IN

IN

IN

IN

IN

IN

GND

VCC

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

IN

5

6

7

8

9

10

11

25

24

23

22

21

20

19

IN/PD

IN

IN

GND*

IN

IN

IN

I/O

I/O

I/O

GND*

I/O

I/O

I/O