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IS-705RH Arkusz danych(PDF) 2 Page - Intersil Corporation |
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IS-705RH Arkusz danych(HTML) 2 Page - Intersil Corporation |
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2 / 2 page ![]() 2 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Die Characteristics DIE DIMENSIONS: 1500 µm x 1830µm (59 mils x 72 mils) Thickness: 483 µm ±25.4µm (19 mils ±1 mil) INTERFACE MATERIALS Glassivation Type: Nitride (Si3N4) over Silox (SiO2) Nitride Thickness: 4.0kÅ ±1.0kÅ Silox Thickness: 12.0kÅ ±4.0kÅ Top Metallization Top Metal 3: TiAlCu Thickness: 0.8 µm ±0.02µm Metal 1 and 2: TiAlCu Thickness: 0.4 µm ±0.01µm Substrate: UHF2X-CMOS Backside Finish: Silicon ASSEMBLY RELATED INFORMATION Substrate Potential: Backside internally connected to GND (May be left floating or connected to GND.) ADDITIONAL INFORMATION Worst Case Current Density: <2.0 x 105 A/cm2 Metallization Mask Layout IS-705RH NOTES: 1. Octagonal trim pads should be left unconnected. VCC (2) GND (3) PFI (4) PFO (5) WDI (6) RESET (7) WDO (8) MR (1) IS-705RH |
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