PCF8532 datasheet(14/44 Pages) NXP

14 / 44 page

PCF8532_1

Product data sheet

Rev. 1 — 10 February 2009

14 of 44

NXP Semiconductors

PCF8532

Universal LCD driver for low multiplex rates

7.9 Backplane outputs

The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane

output signals are generated in accordance with the selected LCD drive mode.

• In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD.

If less than four backplane outputs are required the unused outputs can be left

open-circuit.

• In 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same

signals and may also be paired to increase the drive capabilities.

• In static drive mode the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

The pins for the four backplanes BP0 to BP3 are available on both pin bars of the chip. In

applications it is possible to use either the pins for the backplanes

• on the top pin bar

• on the bottom pin bar

• or both of them to increase the driving strength of the device.

When using all backplanes available they may be connected to the respective sibling (BP0

on the top pin bar with BP0 on the bottom pin bar and so on).

7.10 Display RAM

The display RAM is a static 160

× 4-bit RAM which stores LCD data. A logic 1 in the RAM

bit map indicates the on-state of the corresponding LCD element (it is shaded); similarly, a

logic 0 indicates the off-state (it is translucent). There is a one-to-one correspondence

between the RAM addresses and the segment outputs and between the individual bits of

a RAM word and the backplane outputs. The ﬁrst RAM row corresponds to the

160 elements operated with respect to backplane BP0 (see Figure 9). In multiplexed LCD

applications the segment data of the ﬁrst, second, third and fourth row of the display RAM

are time-multiplexed with BP0, BP1, BP2 and BP3 respectively.

When display data is transmitted to the PCF8532 the display bytes received are stored in

the display RAM in accordance with the selected LCD drive mode. The data is stored as it

arrives and does not wait for the acknowledge cycle as with the commands. Depending on

the current multiplex mode data is stored singularly, in pairs, triplets or quadruplets, e.g. in

1:2 multiplex mode the RAM data is stored every second bit. To illustrate the ﬁlling order,

an example of a 7-segment numeric display showing all drive modes is given in Figure 10;

the RAM ﬁlling organization depicted applies equally to other LCD types.

The following applies to Figure 10:

• In static drive mode the eight transmitted data bits are placed in row 0 to eight

successive display RAM addresses.

• In 1:2 multiplex mode the eight transmitted data bits are placed in row 0 and 1 to four

successive display RAM addresses.

PCF8532 Arkusz danych(PDF) 14 Page - NXP Semiconductors

PCF8532 Arkusz danych(HTML) 14 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Arkusz danych Pobierz

Link URL