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M95320 Arkusz danych(PDF) 30 Page - STMicroelectronics |
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M95320 Arkusz danych(HTML) 30 Page - STMicroelectronics |
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30 / 44 page ![]() DC and AC parameters M95320, M95320-W, M95320-R 30/44 Doc ID 5711 Rev 12 Table 17. AC characteristics (M95320, device grade 3) Test conditions specified in Table 10 and Table 11 Symbol Alt. Parameter Min. Max. Min.(1) Max.(1) Unit fC fSCK Clock frequency D.C. 5 D.C. 10 MHz tSLCH tCSS1 S active setup time 90 30 ns tSHCH tCSS2 S not active setup time 90 30 ns tSHSL tCS S deselect time 100 40 ns tCHSH tCSH S active hold time 90 30 ns tCHSL S not active hold time 90 30 ns tCH (2) tCLH Clock high time 90 42 ns tCL (2) tCLL Clock low time 90 40 ns tCLCH (3) tRC Clock rise time 1 2 µs tCHCL (3) tFC Clock fall time 1 2 µs tDVCH tDSU Data in setup time 20 10 ns tCHDX tDH Data in hold time 30 10 ns tHHCH Clock low hold time after HOLD not active 70 30 ns tHLCH Clock low hold time after HOLD active 40 30 ns tCLHL Clock low set-up time before HOLD active 0 0 ns tCLHH Clock low set-up time before HOLD not active 0 0 ns tSHQZ (3) tDIS Output disable time 100 40 ns tCLQV (4) tV Clock low to output valid 60 40 ns tCLQX tHO Output hold time 0 0 ns tQLQH (3) tRO Output rise time 50 40 ns tQHQL (3) tFO Output fall time 50 40 ns tHHQV tLZ HOLD high to output valid 50 40 ns tHLQZ (3) tHZ HOLD low to output high-Z 100 40 ns tW tWC Write time 5 5 ms 1. These timings are offered with grade3 devices referenced with “/PC” process letters only (see the last digits in the Part numbering). 2. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 3. Value guaranteed by characterization, not 100% tested in production. 4. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU. |
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