L9950 datasheet(26/39 Pages) STMICROELECTRONICS

26 / 39 page

Functional description of the SPI

L9950 - L9950XP

26/39

Doc ID 10311 Rev 10

4.8

Test mode

The test mode can be entered by rising the CSN input to a voltage higher than 7.0 V. In the

test mode the inputs CLK, DI, PWM1/2 and the internal 2 MHz CLK can be multiplexed to

data output DO for testing purpose. Furthermore the over-current thresholds are reduced by

a factor of 4 to allow EWS testing at lower current. For EWS testing a special test pad is

available to measure the internal bandgap voltage, the TW and TSD thresholds.

The internal logic prevents that the Hi-Side and Lo-Side driver of the same half-bridge can

be switched on at the same time. In the test mode this combination is used to multiplex the

desired signals according to following table:

Table 18.

Test mode

LS1 HS1 LS2 HS2 LS3 HS3

LS3 HS3 LS4 HS4 LS5 HS5

Test pad

! (both HI)

No error

! (both HI)

5µA Iref

both HI

! (both HI)

both HI

! (both HI)

Tsens1

! (both HI)

both HI

! (both HI)

CLK

! (both HI)

both HI

! (both HI)

Tsens2

both HI

! (both HI)

INT_CLK

both HI

! (both HI)

Tsens3

! (both HI)

both HI

PWM1

! (both HI)

both HI

Tsens4

both HI

! (both HI)

both HI

PWM2

both HI

! (both HI)

both HI

Tsens5

! (both HI)

both HI

Tsens6

both HI

Vbandgap

L9950 Arkusz danych(PDF) 26 Page - STMicroelectronics

L9950 Arkusz danych(HTML) 26 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Arkusz danych Pobierz

Link URL