STM802MDS6F datasheet(8/43 Pages) STMICROELECTRONICS

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Description

STM690A/692A/703/704/802/805/817/818/819

8/43

Doc ID 10522 Rev 10

Figure 5.

STM703/704/819 connections

Figure 6.

STM818 connections

1.1

Pin descriptions

1.1.1

A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low

and for trec after MR returns high. This active-low input has an internal pull-up. It can be

driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if

unused.

1.1.2

WDI

If WDI remains high or low for 1.6 sec, the internal watchdog timer runs out and reset is

triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a

rising or falling edge.

The watchdog function can be disabled by allowing the WDI pin to float.

1.1.3

RST

Pulses low for trec when triggered, and stays low whenever VCC is below the reset threshold

or when MR is a logic low. It remains low for trec after either VCC rises above the reset

threshold, the watchdog triggers a reset, or MR goes from low to high.

1.1.4

RST

Pulses high for trec when triggered, and stays high whenever VCC is above the reset

threshold or when MR is a logic high. It remains high for trec after either VCC falls below the

reset threshold, the watchdog triggers a reset, or MR goes from high to low.

PFO

PFI

RST

VCC

VOUT

VBAT

VSS

AI07890

SO8/TSSOP8

ECON

WDI

RST

VCC

VOUT

VBAT

VSS

AI07892

SO8/TSSOP8

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