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L9803 Arkusz danych(PDF) 102 Page - STMicroelectronics

Numer części L9803
Szczegółowy opis  Super smart power motor driver with 8-Bit MCU, RAM, EEPROM, ADC, WDG, Timers, PWM and H-bridge driver
PDF  126 Pages
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9803 Arkusz danych(HTML) 102 Page - STMicroelectronics

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On-Chip Peripherals
L9803
102/126
At the end of the programming cycle, the E2PGM and E2LAT bits are cleared
simultaneously, and an interrupt is generated if the IE bit is set. The Data EEPROM interrupt
request is cleared by hardware when the Data EEPROM interrupt vector is fetched.
Wait mode
The EEPROM can enter the wait mode by executing the wait instruction of the micro-
controller. The EEPROM will effectively enter this mode if there is no programming in
progress, in such a case the EEPROM will finish the cycle and then enter this low
consumption mode.
Halt mode
The EEPROM enters the halt mode if the micro-controller did execute the halt instruction.
The EEPROM will stop the function in progress, and will enter in this low consumption mode.
Figure 48.
Data EEPROM Programming Cycle
Figure 49.
EEPROM Programming Flowchart
E2LAT
ERASE CYCLE
WRITE CYCLE
E2PGM
tPROG
READ OPERATION NOT POSSIBLE
WRITE OF
DATA LATCHES
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
EEPROM INTERRUPT
E2LAT=1
E2PGM=0
Write bytes in
EEPROM
E2LAT=1
E2PGM=1
(Start
programming
cycle)
Wait for end of
programming
(E2LAT=0
or interrupt)
Write 1 to 4 bytes
in the same row
(with the same 12
Most Significant
Bits of the ad-
E2LAT=0
E2PGM=0
(Read mode)



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