ADSP-BF504 datasheet(41/80 Pages) AD

41 / 80 page

Preliminary Technical Data

Rev. PrC

Page 41 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Serial Peripheral Interface (SPI) Port—Master Timing

Table 32 and Figure 21 describe SPI port master operations.

Table 32. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter

DDEXT = 1.8 V

DDEXT = 2.5/3.3 V

Min

Max

Min

Max

Unit

Timing Requirements

tSSPIDM

Data Input Valid to SCK Edge (Data Input Setup)

12.0

11.6

tHSPIDM

SCK Sampling Edge to Data Input Invalid

–1.5

Switching Characteristics

tSDSCIM

SPISELx low to First SCK Edge

2 × tSCLK –1.5

tSPICHM

Serial Clock High Period

2 × tSCLK –1.5

tSPICLM

Serial Clock Low Period

2 × tSCLK –1.5

tSPICLK

Serial Clock Period

4 × tSCLK –1.5

tHDSM

Last SCK Edge to SPISELx High

2 × tSCLK –1.5

tSPITDM

Sequential Transfer Delay

2 × tSCLK –1.5

2 × tSCLK–1.5

tDDSPIDM

SCK Edge to Data Out Valid (Data Out Delay)

tHDSPIDM

SCK Edge to Data Out Invalid (Data Out Hold)

–1.0

Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing

tSPICHM

tSDSCIM

tSPICLM

tSPICLK

tHDSM

tSPITDM

tSPICLM

tSPICHM

MSB

VALID

LSB VALID

MSB VALID

LSB

MSB

tHDSPIDM

tHSPIDM

tSSPIDM

LSB VALID

SPISELx

(OUTPUT)

SCK

(CPOL = 0)

(OUTPUT)

SCK

(CPOL = 1)

(OUTPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

CPHA = 1

CPHA = 0

tDDSPIDM

tHSPIDM

tSSPIDM

tHDSPIDM

tDDSPIDM

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