MSC8252 datasheet(55/68 Pages) FREESCALE

55 / 68 page

Hardware Design Considerations

MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3

Freescale Semiconductor

3.1.4

Reset Guidelines

When a debugger is not used, implement the connection scheme shown in Figure 35.

When a debugger is used, implement the connection scheme shown in Figure 36.

3.2

PLL Power Supply Design Considerations

Each global PLL power supply must have an external RC filter for the PLLn_AVDD input (see Figure 37) in which the

following components are defined as listed:

•R = 5

Ω ± 5%

•C1 = 10 µF

± 10%, 0603, X5R, with ESL

≤ 0.5 nH, low ESL Surface Mount Capacitor.

•

C2 = 1.0 µF

± 10%, 0402, X5R, with ESL

≤ 0.5 nH, low ESL Surface Mount Capacitor.

Note:

A higher capacitance value for C2 may be used to improve the filter as long as the other C2 parameters do not change.

All three PLLs can connect to a single supply voltage source (such as a voltage regulator) as long as the external RC filter is

applied to each PLL separately. For optimal noise filtering, place the circuit as close as possible to its PLLn_AVDD inputs.

Figure 35. Reset Connection in Functional Application

Figure 36. Reset Connection in Debugger Application

On-board PORESET source

TRST

PORESET

MSC815x

(example: voltage monitor)

ΚΩ

On-board PORESET source

TRST

PORESET

MSC815x

(example: voltage monitor)

On-board TRST source

(example: OnCE)

VDDIO

MSC8252 Arkusz danych(PDF) 55 Page - Freescale Semiconductor, Inc