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STM8L151C4U6 Arkusz danych(PDF) 100 Page - STMicroelectronics |
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STM8L151C4U6 Arkusz danych(HTML) 100 Page - STMicroelectronics |
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100 / 122 page ![]() Electrical parameters STM8L151xx, STM8L152xx 100/122 Doc ID 15962 Rev 5 Data guaranteed by design, not tested in production. 9.3.12 12-bit DAC characteristics Data guaranteed by design, not tested in production. Table 47. Comparator 2 characteristics Symbol Parameter Min Typ Max Unit VDDA Analog supply voltage 1.65 3.6 V TA Temperature range -40 125 °C VIN Comparator input voltage range 0 VDDA V tSTART Startup time after enable in fast mode 20 µs Startup time after enable in slow mode 30 µs tdf Propagation delay in fast mode(1) 1. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non- inverting input set to the reference. 2.5 µs tds Propagation delay in slow mode(1) 6µs Voffset Comparator offset error ±10 mV IDD(CMP2F) Consumption in fast mode 5 µA IDD(CMP2S) Consumption in slow mode 2 µA Table 48. DAC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage 1.8 3.6 V TA Temperature range -40 125 °C IDD(DAC) (1) DAC supply current Middle code 370 550 µA Worst code 500 700 IVREF+ Current on VREF+ supply 140 360 µA RL Resistive load(2) (3) DACOUT buffer ON 5 k Ω RO Output impedance DACOUT buffer OFF 8 10 k Ω CL Capacitive load(4) 50 pF DAC_OUT DAC_OUT voltage(5) DACOUT buffer ON 0.2 VREF+-0.2 V DACOUT buffer OFF 0 VREF+ -1 LSB V tsettling Settling time (full scale: for a 12- bit input code transition between the lowest and the highest input codes when DAC_OUT reaches the final value ±1LSB ) RL ≥5kΩ, CL≤ 50 pF 712 µs Update rate Max frequency for a correct DAC_OUT (@95%) change when small variation of the input code (from code i to i+1LSB). RL ≥ 5kΩ, CL ≤50 pF 1 Msps |
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