Analog Integrated Circuit Device Data

12

Freescale Semiconductor

33882

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

SI Setup to Rising Edge (2.0 V) of SCLK (at 3.2 MHz)

Required Setup Time (36)

–

–

45

ns

SO Setup to SCLK Rising (2.0 V)/Falling (0.8 V) Edge

Required Setup Time (36)

90

–

–

ns

SI Hold After Rising Edge (2.0 V) of SCLK (at 3.2 MHz)

Required Hold Time (36)

–

–

45

ns

SO Hold After SCLK Rising (2.0 V)/Falling (0.8 V) Edge

Required Hold Time (36)

90

–

–

ns

SO Rise Time

–

–

50

ns

SO Fall Time

–

–

50

ns

–

–

110

ns

–

–

110

ns

Falling Edge of SCLK (0.8 V) to SO Data Valid

–

65

80

ns

CS

Rising Edge to Next Falling Edge (36)

Xfer DELAY

–

–

1.0

Notes

36.

Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.

37.

Enable time required for SO. Pull-up resistor = 10 k

Ω.

38.

Disable time required for SO. Pull-up resistor = 10 k

Ω.

39.

Time required to obtain valid data out of SO following the falling edge of SCLK.

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V

noted.

Characteristic

Symbol

Min

Typ

Max

Unit