MPC5643L_11 datasheet(21/124 Pages) FREESCALE

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Introduction

MPC5643L Microcontroller Data Sheet, Rev. 6

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

—JCOMP

•

Selectable modes of operation include JTAGC/debug or normal system operation

•

5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

—BYPASS

— IDCODE

—EXTEST

—SAMPLE

— SAMPLE/PRELOAD

•

3 test data registers: a bypass register, a boundary scan register, and a device identification register. The size of the

boundary scan register is parameterized to support a variety of boundary scan chain lengths.

•

TAP controller state machine that controls the operation of the data registers, instruction register and associated

circuitry

1.6.40

Voltage regulator / Power Management Unit (PMU)

The on-chip voltage regulator module provides the following features:

•

Single external rail required

•

Single high supply required: nominal 3.3 V both for packaged and Known Good Die option

— Packaged option requires external ballast transistor due to reduced dissipation capacity at high temperature but

can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower

frequency of operation)

— Known Good Die option uses embedded ballast transistor as dissipation capacity is increased to reduce system

cost

•

All I/Os are at same voltage as external supply (3.3 V nominal)

•

Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages (reset, configuration, normal

operation) and, to maximize safety coverage, one LVD can be tested while the other operates (on-line self-testing

feature)

1.6.41

Built-In Self-Test (BIST) capability

This device includes the following protection against latent faults:

•

Boot-time Memory Built-In Self-Test (MBIST)

•

Boot-time scan-based Logic Built-In Self-Test (LBIST)

•

Run-time ADC Built-In Self-Test (BIST)

•

Run-time Built-In Self Test of LVDs

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