2

SPDT High Isolation Terminated Switch

0.01 - 3.0 GHz

Rev. V7

MASWSS0024

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changes to the product(s) or information contained herein without notice.

ADVANCED: Data Sheets contain information regarding a product M/A-COM Technology Solutions

is considering for development. Performance is based on target specifications, simulated results,

and/or prototype measurements. Commitment to develop is not guaranteed.

PRELIMINARY: Data Sheets contain information regarding a product M/A-COM Technology

Solutions has under development. Performance is based on engineering tests. Specifications are

typical. Mechanical outline has been fixed. Engineering samples and/or test data may be available.

Commitment to produce in volume is not guaranteed.

5

Parameter

Test Conditions

Units

Min.

Typ.

Max.

Insertion Loss

0.01 - 0.5 GHz

0.5 - 1.0 GHz

1.0 - 2.0 GHz

2.0 - 3.0 GHz

dB

—

—

—

—

0.5

0.6

0.7

0.75

—

0.7

0.8

—

Isolation

0.01 - 0.5 GHz

0.5 - 1.0 GHz

1.0 - 2.0 GHz

2.0 - 3.0 GHz

dB

—

51

44

—

59

57

53

43

—

—

—

—

Return Loss

0.5 - 1.0 GHz

1.0 - 2.0 GHz

2.0 - 3.0 GHz

dB

—

—

—

—

20

20

20

20

—

—

—

—

2-Tone, 900 MHz, 5 MHz spacing

dBm

—

83

—

2-Tone, 900 MHz, 5 MHz spacing

dBm

—

43

—

Trise, Tfall

10% to 90% RF & 90% to 10% RF

ns

—

24

—

Ton, Toff

ns

—

15

—

Transients

In-band

mV

—

12

—

Control Current

µA

—

2

13

Input P1dB Compression

dBm

—

—

29

17.5

—

—

Handling Procedures

Please observe the following precautions to avoid

damage:

Static Sensitivity

Gallium Arsenide Integrated Circuits are sensitive

to electrostatic discharge (ESD) and can be

damaged by static electricity. Proper ESD control

techniques should be used when handling these

devices.

Truth Table

V1

V2

RFC-RF1

RFC-RF2

0

1

Off

On

1

0

On

Off

Logic Level

Voltage Level

0 ± 0.2 V

3.0 V to 8.0 V

5. External DC blocking capacitors are required on all RF ports (47 pF capacitors are recommended). Use larger value capacitors for lower

frequency operation (e.g. use 10,000 pF capacitors to optimize insertion and return loss at frequencies below 50 MHz).

6. Terminated return loss is governed by blocking capacitors internal to the device; see applications plot.