FULLFLEX datasheet(28/52 Pages) CYPRESS

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FullFlex

Document Number: 38-06082 Rev. *K

Page 28 of 52

Table 15. Master Reset Timing

Parameter

Description

-200

-167

Unit

Min

Max

Min

Max

tPUP

Power-up time

–

tRS

Master reset pulse width

–

cycles

tRSR

Master reset recovery time

–

cycles

tRSF

Master reset to outputs inactive/Hi Z

–

tRDY[54]

Master reset release to port ready

–

1024

–

1024

cycles

tCORDY[55]

C rise to port ready

–

9.5[56]

–11[56]

Table 16. JTAG Timing

Parameter

Description

-200

-167

Unit

Min

Max

Min

Max

fJTAG

JTAG TAP controller frequency

–

MHz

tTCYC

TCK cycle time

50–50–

tTH

TCK high time

–

tTL

TCK low time

20–20–

tTMSS

TMS setup to TCK rise

–

tTMSH

TMS hold to TCK rise

10–10–

tTDIS

TDI setup to TCK rise

–

tTDIH

TDI hold to TCK rise

–

tTDOV

TCK low to TDO valid

–

tTDOX

TCK low to TDO invalid

–

tJXZ

TCK low to TDO high Z

–

tJZX

TCK low to TDO active

–15–15

tJZX

TCK low to TDO active

–15–15

Notes

54. READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250-

 resistor to VSS.

55. Add this propagation delay after tRDY for all Master Reset Operations.

56. Add 15% to this parameter if a VCORE of 1.5 V is used.

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