SC1402 datasheet(9/18 Pages) SEMTECH

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SC1402

652 MITCHELL ROAD

NEWBURY PARK CA 91320

Multi-Output, Low-Noise Power Supply

Controller for Notebook Computers

December 15, 2000

FET gate charge current). The VL pin should be by-

passed to GND with 4.7uF to supply the peak current

requirements of the gate driver outputs.

This regulator receives its input power from the V+ bat-

tery input. Efficiency is improved by providing a boot-

strapping mode for the VL bias. When the 5V SMPS

output voltage reaches 5V, internal circuitry detects

this condition and turns on a PMOS pass device be-

tween CSL5 and VL. The internal VL regulator is then

disabled and the VL bias is provided by the high effi-

ciency switch mode power supply.

The REF output is accurate to +/- 2% over tempera-

ture. It is capable of delivering 5mA max and should

be bypassed with 1uF minimum capacitor. Loading the

REF output will reduce the REF voltage slightly.

Current Sense (CSH,CSL)

The output current of the power supply is sensed as

the voltage drop across an external resistor between

the CSH and CSL pins. Over-current is detected when

the current sense voltage exceeds +/-100mV. The

negative current limit (i.e. -100mV) is required for oper-

ation with PSAVE mode disabled, and also to limit the

output current when charging the bulk supply capacitor

of the 12V regulator. A positive over-current will turn

off the high-side driver, a negative over-current will turn

off the low-side driver, each on a cycle by cycle basis.

The current sense is also used for peak current feed

back in the main PWM loop and for determining the

current level for entering power save mode and the

turn off time for the synchronous rectifier.

Oscillator

The SC1402 oscillator frequency is trimmed to +/-

10%. When the SYNC pin is set high the oscillator

runs at 300kHz; when SYNC is set low the frequency is

200kHz. The oscillator can also be synchronized to

the falling edge of a clock on the SYNC pin with a fre-

quency between 240kHz and 350kHz. In general,

200kHz operation is used for highest efficiency, and

the 300kHz for minimum output ripple and/or smaller

inductor and output capacitor sizes.

Fault Protection

In addition to cycle-by-cycle current limit, the SC1402

monitors over-temperature, and output over-voltage

and under-voltage conditions. The over-temperature

detect will shut the part down if the die temperature ex-

ceeds 150°C with 10°C of hysteresis.

If either SMPS output is greater than 7% above its

nominal value, both SMPS are latched off and syn-

chronous rectifiers are latched on. To prevent the out-

put from ringing below, ground a 1A Schottky diode

should be placed across each output, anode at GND.

Two different levels of undervoltage are detected. If the

output falls 5% below its nominal output, the RESET

output is pulled low. If the output falls 30% below its

nominal output following a startup delay, both SMPS

are latched off.

Both of the latched fault modes will remain in effect un-

til SHDN or RUN/ON3 is toggled or the V+ input is

brought below 1V.

Shutdown and Operating Modes

Holding the SHDN pin low disables the SC1402, reduc-

ing the V+ input current to <10uA. When SHDN goes

high, the part enters a standby mode where the VL

regulator and VREF are enabled. Turning on either

SMPS will put the SC1402 in run mode.

Output Voltage Selection

If FB is connected to ground, internal resistors setup

3.3V and 5V output voltages. If external resistors are

used, the internal feedback is disabled and the output

is regulated based on 2.5V at the FB pin.

12OUT Supply

The 12OUT linear regulator is capable of supplying

120mA. The input voltage to the 12OUT regulator is

generated by a secondary winding on the 5V SMPS

SHDN

RUN/

ON3

TIME/

ON5

MODE

DESCRIPTION

Low

Shut-

down

Minimum bias

current

High

Low

Standby

VREF and VL

regulator

enabled

High

Run

Mode

Both SMPS

Running

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