ADP151ACBZ-1.8-R7 datasheet(21/24 Pages) AD

21 / 24 page

ADP151

Rev. D | Page 21 of 24

OUTLINE DIMENSIONS

*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

1.60 BSC

2.80 BSC

1.90

BSC

0.95 BSC

0.20

0.08

0.60

0.45

0.30

8°

4°

0°

0.50

0.30

0.10 MAX

*1.00 MAX

*0.90 MAX

0.70 MIN

2.90 BSC

SEATING

PLANE

Figure 63. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)

Dimensions show in millimeters

0.050 NOM

COPLANARITY

0.800

0.760 SQ

0.720

0.230

0.200

0.170

0.280

0.260

0.240

0.660

0.600

0.540

0.430

0.400

0.370

BOTTOM VIEW

(BALL SIDE UP)

TOP VIEW

(BALL SIDE DOWN)

SEATING

PLANE

0.40

BALL PITCH

BALL A1

IDENTIFIER

Figure 64. 4-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-4-3)

Dimensions show in millimeters

1.70

1.60

1.50

0.425

0.350

0.275

TOP VIEW

0.35

0.30

0.25

BOTTOM VIEW

PIN 1 INDEX

AREA

SEATING

PLANE

0.60

0.55

0.50

1.10

1.00

0.90

0.20 REF

0.05 MAX

0.02 NOM

2.00

BSC SQ

0.65 BSC

EXPOSED

PAD

PIN 1

INDICATOR

(R 0.15)

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

Figure 65. 6-Lead Lead Frame Chip Scale Package [LFCSP_UD]

2.00 mm × 2.00 mm Body, Ultra Thin, Dual Lead

(CP-6-3)

Dimensions show in millimeters

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