GS7025 PRO-LINX™ Serial Digital Receiver

Data Sheet

13813 - 7

October 2009

16 of 23

3.2.4 Locking

The GS7025 indicates valid lock when the following three conditions are satisfied:

1. Input data is detected.

2. The incoming data signal and the PLL clock are phase locked.

3. The system is not locked to an integer-multiple harmonic of a 270Mb/s SMPTE

259M-C signal.

The GS7025 defines the presence of input data when at least one data transition occurs

every 1μs.

The GS7025 assumes that it is NOT locked to a harmonic if the pattern ‘101’ or ‘010’ (in

the reclocked data stream) occurs at least once every tsys/3 seconds. Using the

recommended component values, this corresponds to approximately 150μs. In a

harmonically locked system, all bit cells are double clocked and the above patterns

become ‘110011’ and ‘001100’, respectively.

3.2.4.1 Lock Time

Synchronous switching refers to the case where the input data is changed from one

source to another source which is at the same data rate (but different phase).

When input data to the GS7025 is removed, the GS7025 latches the current state.

Therefore, when data is reapplied, the GS7025 begins the lock procedure at the previous

locked data rate. As a result, in synchronous switching applications, the GS7025 locks

very quickly. The nominal lock time depends on the switching time and is summarized

in Table 3-2.

To acquire lock, the frequency acquisition circuit may have to sweep over an entire

cycle depending on initial conditions. Maximum lock time is 2Tcycle + 2tsys.

The nominal value of Tcycle for the GS7025 operating in a typical SMPTE 259M-C

application is approximately 1.3ms.

The GS7025 has a dedicated LOCK output (pin 39) indicating when the device is locked.

Note: In synchronous switching applications where the switching time is less than 0.5μs,

the LOCK output is not de-asserted and the data outputs are not muted.

3.2.4.2 DVB-ASI

Design Note: For DVB-ASI applications having significant instances of few bit

transitions or when only K28.5 idle bits are transmitted, the wide-band PLL in the

Table 3-2: Lock Time

Switching Time

Lock Time

<0.5µs

10µs

0.5µs - 10ms

>10ms