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L3GD20TR Arkusz danych(PDF) 15 Page - STMicroelectronics |
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L3GD20TR Arkusz danych(HTML) 15 Page - STMicroelectronics |
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15 / 44 page  L3GD20 Application hints Doc ID 022116 Rev 1 15/44 3 Application hints Figure 5. L3GD20 electrical connections and external component values Power supply decoupling capacitors (100 nF + 10 µF) should be placed as near as possible to the device (common design practice). If Vdd and Vdd_IO are not connected together, 100 nF and 10 µF decoupling capacitors must be placed between Vdd and common ground, and 100 nF between Vdd_IO and common ground. Capacitors should be placed as near as possible to the device (common design practice). 9nF 100 nF Vdd GND C1 GND 10 µF SCL/SPC CS DR SDO/SA0 SDA_SDI_SDO 10nF(25V)* Vdd_IO 1 8 12 5 49 13 16 TOP VIEW INT (TOP VIEW) DIRECTIONS OF THE DETECTABLE ANGULA RATES X +Ω Z +Ω X +Ω Y Vdd I2C bus Rpu = 10kOhm Rpu SCL/SPC SDA_SDI_SDO Pull-up to be added when I2C interface is used 14 GND * C1 must guarantee 1 nF value under 11 V bias condition AM10128V1 |
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