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ICS9LPRS464 Arkusz danych(PDF) 7 Page - Integrated Device Technology |
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ICS9LPRS464 Arkusz danych(HTML) 7 Page - Integrated Device Technology |
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7 / 23 page  7 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 1377A—04/07/08 AC Electrical Characteristics - Low-Power DIF Outputs: SRC and ATIG PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Rising Edge Slew Rate t SLR Differential Measurement 0.5 2 V/ns 1,2 Falling Edge Slew Rate t FLR Differential Measurement 0.5 2 V/ns 1,2 Slew Rate Variation t SLVAR Single-ended Measurement 20 % 1 Maximum Output Voltage V HIGH Includes overshoot 1150 mV 1 Minimum Output Voltage V LOW Includes undershoot -300 mV 1 Differential Voltage Swing V SWING Differential Measurement 300 mV 1 Crossing Point Voltage V XABS Single-ended Measurement 300 550 mV 1,3,4 Crossing Point Variation V XABSVAR Single-ended Measurement 140 mV 1,3,5 Duty Cycle D CYC Differential Measurement 45 55 % 1 SRC, ATIG, Jitter - Cycle to Cycle SRCJ C2C Differential Measurement 125 ps 1 SRC[5:0] Skew SRC SKEW Differential Measurement 250 ps 1 SB_SRC[1:0] Skew SRC SKEW Differential Measurement 100 ps 1 ATIG[3:0] Skew SRC SKEW Differential Measurement 100 ps 1 1Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 Only applies to the differential rising edge (CLK rising and CLK# falling) 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of Electrical Characteristics - USB - 48MHz PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -100 100 ppm 1,2 Clock period Tperiod 48.00MHz output nominal 20.8229 20.8344 ns 2 Clock Low Time Tlow Measure from < 0.6V 9.3750 11.4580 ns 2 Clock High Time Thigh Measure from > 2.0V 9.3750 11.4580 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL IOL = 1 mA 0.55 V 1 V OH @MIN = 1.0 V -33 mA 1 VOH@MAX = 3.135 V -33 mA 1 VOL @ MIN = 1.95 V 30 mA 1 VOL @ MAX = 0.4 V 38 mA 1 Rise Time tr_USB VOL = 0.4 V, VOH = 2.4 V 0.5 1.5 ns 1 Fall Time tf_USB VOH = 2.4 V, VOL = 0.4 V 0.5 1.5 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 %1 Group Skew tskew VT = 1.5 V 250 ps 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 130 ps 1,2 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 33 Ω (unless otherwise specified) 1Guaranteed by design and characterization, not 100% tested in production. 2ICS recommended and/or chipset vendor layout guidelines must be followed to meet this specification Output Low Current IOL Output High Current IOH |
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