HT95R34 datasheet(39/59 Pages) HOLTEK

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HT95R34

Rev. 1.10

February 18, 2009

Steering Time Adjustment Circuits

Programmable Frequency Divider (PFD) Generator

- MUSIC

A Programmable Frequency Divider function, otherwise known as PFD, is integrated within the microcontroller, provid-

ing a means of accurate frequency generation. It is composed of two functional blocks: a prescaler and a general coun-

ter.

PFD Control Register

The overall PFD function is controlled using the PFDC register. The prescaler is controlled by the register bits, PRES0

and PRES1. The general counter is programmed by an 8-bit register PFDD. The clock source for the PFD can be se-

lected to be either the 3.58MHz/4 or the 32768Hz oscillator. To enable the PFD output, the PFDEN bit should be set to

1. When the PFD is disabled the PFDD register is inhibited to be written to. To modify the PFDD contents, the PFD must

be enabled. When the generator is disabled, the PFDD is cleared by hardware.

P r e s c a l e r

O u t p u t

P F D D

P R E S 1 , P R E S 0

3 2 7 6 8 H z

3 . 5 8 M H z / 4

P F D E N

P F D

O u t p u t

M U S I C

B u z z e r

P F D C R e g i s t e r

b 0

N o t i m p l e m e n t e d , r e a d a s " 0 "

b 7

P F D O u t p u t E n a b l e

1 : e n a b l e

0 : d i s a b l e

P F D P r e s c a l e r S e l e c t

0 0 : P r e s c a l e r o u t p u t = P F D f r e q u e n c y s o u r c e / 1

0 1 : P r e s c a l e r o u t p u t = P F D f r e q u e n c y s o u r c e / 2

1 0 : P r e s c a l e r o u t p u t = P F D f r e q u e n c y s o u r c e / 4

1 1 : P r e s c a l e r o u t p u t = P F D f r e q u e n c y s o u r c e / 8

P F D F r e q u e n c y S o u r c e S e l e c t

1 : 3 . 5 8 M H z / 4

0 : 3 2 7 6 8 H z

F P F D

P R E S 1 P R E S 0 P F D E N

V D D

R T / G T

E S T

V D D

(a) Fundamental circuit:

tGTP =R

´ C ´ Ln (VDD /(VDD - VTRT))

tGTA =R

´ C ´ Ln (VDD /VTRT)

R 1

V D D

R T / G T

E S T

R 2

D 1

V D D

(b) tGTP <tGTA :

tGTP = (R1 // R2)

´ C ´ Ln (VDD - VTRT))

tGTA =R1

´ C ´ Ln (VDD /VTRT)

R 1

V D D

R T / G T

E S T

R 2

D 1

V D D

tGTP =R1

´ C ´ Ln (VDD /(VDD - VTRT))

tGTA = (R1 // R2)

´ C ´ Ln (VDD /VTRT)

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